/*
 *Copyright (c) 2024 Black Sesame Technologies
 *
 *Licensed under the Apache License, Version 2.0 (the "License");
 *you may not use this file except in compliance with the License.
 *You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 *Unless required by applicable law or agreed to in writing, software
 *distributed under the License is distributed on an "AS IS" BASIS,
 *WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *See the License for the specific language governing permissions and
 *limitations under the License.
*/
#ifndef C1200_SW_CRM_CSR_TABLE_H
#define C1200_SW_CRM_CSR_TABLE_H
#define SW_CRM_CSR_BASE_ADDR		(0x217B0000U)

#define WR_PROT_OFFSET              (0x00U)
#define TEST0_OFFSET                (0x10U)
#define TEST1_OFFSET                (0x14U)
#define COLD_RST_OFFSET             (0x20U)
#define WARM_RST_OFFSET             (0x24U)
#define SW_RST_OFFSET               (0x28U)
#define ETH_RST_OFFSET              (0x2cU)
#define WDT_RST_MASK_OFFSET         (0x30U)
#define MAIN_PLL_CTRL_OFFSET        (0x40U)
#define MAIN_PLL_DIV_OFFSET         (0x44U)
#define MAIN_PLL_FRC_DIV_OFFSET     (0x48U)
#define MAIN_PLL_SSC_CTRL_OFFSET    (0x4cU)
#define ETH_PLL_CTRL_OFFSET         (0x50U)
#define ETH_PLL_DIV1_OFFSET         (0x54U)
#define ETH_PLL_FRC_DIV_OFFSET      (0x58U)
#define ETH_PLL_SSC_CTRL_OFFSET     (0x5cU)
#define ETH_PLL_VCO_OFFSET          (0x60U)
#define ETH_PLL_POSTDIV1_OFFSET     (0x64U)
#define ETH_PLL_POSTDIV2_OFFSET     (0x68U)
#define PLL_STA_OFFSET              (0x6cU)
#define PLL_LOCK_MON_OFFSET         (0x70U)
#define PLL_CLK_CTRL_OFFSET         (0x80U)
#define SW_CLK_EN0_OFFSET           (0x84U)
#define SW_CLK_EN1_OFFSET           (0x88U)
#define SW_CLK_SEL0_OFFSET          (0x90U)
#define SW_CLK_SEL1_OFFSET          (0x94U)
#define SW_CLK_SEL2_OFFSET          (0x98U)
#define MODE_SEL_OFFSET             (0xa0U)


#define WR_PROT_WRITE_PROTECT_U32                                      (0xFFFFFFFFUL) /*write protect writing 0x0xC120_C120 to toggle the write protect control, read the regiser to get the write protect control status in bit0.*/
#define WR_PROT_WRITE_PROTECT_SHIFT_U32                                (0U)

#define TEST0_TEST0_U32                                                (0xFFFFFFFFUL) /*test register0*/
#define TEST0_TEST0_SHIFT_U32                                          (0U)

#define TEST1_TEST1_U32                                                (0xFFFFFFFFUL) /*test register1*/
#define TEST1_TEST1_SHIFT_U32                                          (0U)

#define COLD_RST_SW_COLD_RST_U32                                       (0x00000001UL) /*switch subsystem global cold reset, active high 0: no reset 1: reset*/
#define COLD_RST_SW_COLD_RST_SHIFT_U32                                 (0U)

#define WARM_RST_SW_WARM_RST_U32                                       (0x00000001UL) /*switch subsystem global warm reset, active high 0: no reset 1: reset*/
#define WARM_RST_SW_WARM_RST_SHIFT_U32                                 (0U)

#define SW_RST_SW_RST_N_U32                                            (0xFFFFFFFFUL) /*switch subsystem software reset, active low bit0 : switch subsystem r5 core0 reset bit1 : switch subsystem r5 core1 reset bit2 : switch subsystem r5 core2 reset bit3 : switch subsystem r5 core3 reset bit4 : switch subsystem r5 core4 reset bit5 : switch subsystem r5 core5 reset bit6 : switch subsystem r5 core0/1 NIC bus matrix reset bit7 : switch subsystem r5 core2/3 NIC bus matrix reset bit8 : switch subsystem r5 core4/5 NIC bus matrix reset bit9 : switch subsystem system control bus matrix reset bit10: switch subsystem internal sram0 memory reset bit11: switch subsystem internal sram1 memory reset bit12: switch subsystem standby sram memory reset bit13: switch subsystem lsp block reset bit14: switch subsystem CAN apb bus reset bit15: switch subsystem message box reset bit16: switch subsystem DMA reset bit17: switch subsystem AHB NIC bus matrix reset bit18: switch subsystem jiayu merak reset bit19: switch subsystem jiayu axi reset bit20: switch subsystem clock monitor reset bit21: switch subsystem reseverd reset bit22: switch subsystem reseverd reset bit23: switch subsystem PVT reset bit24: switch subsystem reseverd reset bit25: switch subsystem reseverd reset bit26: switch subsystem reseverd reset bit27: switch subsystem reseverd reset bit28: switch subsystem reseverd reset bit29: switch subsystem reseverd reset bit30: switch subsystem reseverd reset bit31: switch subsystem reseverd reset*/
#define SW_RST_SW_RST_N_SHIFT_U32                                      (0U)

#define ETH_RST_ETH_RST_N_U32                                          (0xFFFFFFFFUL) /*switch subsystem ethernet software reset, active low bit0 : switch subsystem ethernet PCS APB bus reset bit1 : switch subsystem ethernet EPP NPU AXI bus reset bit2 : switch subsystem ethernet EPP NPU APB bus reset bit3 : switch subsystem ethernet GMAC reset bit4 : switch subsystem ethernet reseverd reset bit5 : switch subsystem ethernet reseverd reset bit6 : switch subsystem ethernet reseverd reset bit7 : switch subsystem ethernet reseverd reset bit8 : switch subsystem ethernet PCS0 reset bit9 : switch subsystem ethernet PCS1 reset bit10: switch subsystem ethernet PCS2 reset bit11: switch subsystem ethernet PCS3 reset bit12: switch subsystem ethernet reseverd reset bit13: switch subsystem ethernet reseverd reset bit14: switch subsystem ethernet reseverd reset bit15: switch subsystem ethernet reseverd reset bit16: switch subsystem ethernet EPP port 0 XGMAC reset bit17: switch subsystem ethernet EPP port 1 XGMAC reset bit18: switch subsystem ethernet EPP port 2 XGMAC reset bit19: switch subsystem ethernet EPP port 3 XGMAC reset bit20: switch subsystem ethernet EPP port 4 XGMAC reset bit21: switch subsystem ethernet reseverd reset bit22: switch subsystem ethernet reseverd reset bit23: switch subsystem ethernet EPP port 7 XGMAC reset bit24: switch subsystem ethernet EPP port 8 XGMAC reset bit25: switch subsystem ethernet EPP port 9 XGMAC reset bit26: switch subsystem ethernet reseverd reset bit27: switch subsystem ethernet reseverd reset bit28: switch subsystem ethernet reseverd reset bit29: switch subsystem ethernet reseverd reset bit30: switch subsystem ethernet reseverd reset bit31: switch subsystem ethernet reseverd reset*/
#define ETH_RST_ETH_RST_N_SHIFT_U32                                    (0U)

#define MAIN_PLL_CTRL_PLL_MAIN_BYPASS_U32                              (0x00000010UL) /*0 -> Post divided VCO is output on FOUTPOSTDIV 1 -> FREF is bypassed to FOUTPOSTDIV when FOUTPOSTDIVEN =1*/
#define MAIN_PLL_CTRL_PLL_MAIN_BYPASS_SHIFT_U32                        (4U)
#define MAIN_PLL_CTRL_PLL_MAIN_FOUTPOSTDIVEN_U32                       (0x00000008UL) /*Post divide power down 0 -> FOUTPOSTDIV, 4-phase, and synchronous clocks are powered down (outputs held at 1¡¯b0) 1 -> FOUTPOSTDIV, 4-phase, and synchronous clocks are enabled*/
#define MAIN_PLL_CTRL_PLL_MAIN_FOUTPOSTDIVEN_SHIFT_U32                 (3U)
#define MAIN_PLL_CTRL_PLL_MAIN_DSMEN_U32                               (0x00000004UL) /*Enable Delta-Sigma Modulator 0 -> DSM is powered down (integer mode) 1 -> DSM is active (fractional mode)*/
#define MAIN_PLL_CTRL_PLL_MAIN_DSMEN_SHIFT_U32                         (2U)
#define MAIN_PLL_CTRL_PLL_MAIN_DACEN_U32                               (0x00000002UL) /*Enable fractional noise canceling DAC in FRAC mode (this has no  function in integer mode) 0 -> Fractional noise canceling DAC is not active (test mode only) 1 -> Fractional noise canceling DAC is active (default mode)*/
#define MAIN_PLL_CTRL_PLL_MAIN_DACEN_SHIFT_U32                         (1U)
#define MAIN_PLL_CTRL_PLL_MAIN_PLLEN_U32                               (0x00000001UL) /*Global enable signal for PLL 0 -> Entire PLL (except scan mode) is powered down (outputs (except SCANOUT) all held at 1¡¯b0) 1 -> Entire PLL is enabled (unless scan mode is turned on SCANMODE =1)*/
#define MAIN_PLL_CTRL_PLL_MAIN_PLLEN_SHIFT_U32                         (0U)

#define MAIN_PLL_DIV_PLL_MAIN_INTIN_U32                                (0x0FFF0000UL) /*PLL Feedback divide value (16 to 4095 in integer mode, 20 to 4095 in fractional mode)*/
#define MAIN_PLL_DIV_PLL_MAIN_INTIN_SHIFT_U32                          (16U)
#define MAIN_PLL_DIV_PLL_MAIN_POSTDIV2_U32                             (0x00007000UL) /*PLL post divide 2 setting (1 to 7), POSTDIV2=0 is unused Total post divide is POSTDIV1*POSTDIV2, POSTDIV1 >= POSTDIV2*/
#define MAIN_PLL_DIV_PLL_MAIN_POSTDIV2_SHIFT_U32                       (12U)
#define MAIN_PLL_DIV_PLL_MAIN_POSTDIV1_U32                             (0x00000700UL) /*PLL post divide 1 setting (1 to 7), POSTDIV1=0 is unused Total post divide is POSTDIV1*POSTDIV2, POSTDIV1 >= POSTDIV2*/
#define MAIN_PLL_DIV_PLL_MAIN_POSTDIV1_SHIFT_U32                       (8U)
#define MAIN_PLL_DIV_PLL_MAIN_REFDIV_U32                               (0x0000003FUL) /*Reference divide value (1 to 63)*/
#define MAIN_PLL_DIV_PLL_MAIN_REFDIV_SHIFT_U32                         (0U)

#define MAIN_PLL_FRC_DIV_PLL_MAIN_FRACIN_U32                           (0x00FFFFFFUL) /*Fractional portion of feedback divide value*/
#define MAIN_PLL_FRC_DIV_PLL_MAIN_FRACIN_SHIFT_U32                     (0U)

#define MAIN_PLL_SSC_CTRL_PLL_MAIN_DIVVAL_U32                          (0x003F0000UL) /*Input divider to set modulation frequency Divide value is 1 for DIVVAL=6¡¯d0 and DIVVAL for DIVVAL>0 Modulation Freq= F clksscg / (DIVVAL * 128)*/
#define MAIN_PLL_SSC_CTRL_PLL_MAIN_DIVVAL_SHIFT_U32                    (16U)
#define MAIN_PLL_SSC_CTRL_PLL_MAIN_SPREAD_U32                          (0x00001F00UL) /*Spread Depth Control in 0.1% steps 5¡¯b00001 ¨C> 0.1% 5¡¯b00010 ¨C> 0.2% ... 5¡¯b10000 ¨C> 1.6% ... 5¡¯b11111 ¨C> 3.1%*/
#define MAIN_PLL_SSC_CTRL_PLL_MAIN_SPREAD_SHIFT_U32                    (8U)
#define MAIN_PLL_SSC_CTRL_PLL_MAIN_RESETPTR_U32                        (0x00000004UL) /*Active High reset for wave table pointer, Internally synchronized to CLKSSCG 1¡¯b0 ¨C> If modulation is active (RESET=1¡¯b0, DISABLE SSCG=1¡¯b0), INTMOD and FRACMOD are updating based on internal wave table. 1¡¯b1 ¨C> Modulation is stopped and wave table position is reset. INTMOD=INTIN, FRACMOD=FRACIN. Set RESETPTR=1¡¯b1 while Fractional PLL is locking and de-assert after LOCK is established to start modulation*/
#define MAIN_PLL_SSC_CTRL_PLL_MAIN_RESETPTR_SHIFT_U32                  (2U)
#define MAIN_PLL_SSC_CTRL_PLL_MAIN_DOWNSPREAD_U32                      (0x00000002UL) /*Downspread control 1¡¯b0 ¨C> Center-Spread 1¡¯b1 ¨C> Downspread*/
#define MAIN_PLL_SSC_CTRL_PLL_MAIN_DOWNSPREAD_SHIFT_U32                (1U)
#define MAIN_PLL_SSC_CTRL_PLL_MAIN_DISABLE_SSCG_U32                    (0x00000001UL) /*Active-High Modulator Bypass Control 1¡¯b0 ¨C> Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1¡¯b1 ¨C> Bypass modulator (INTMOD = INTIN, FRACMOD = FRACIN). Assertion of DISABLE SSCG is asynchronous*/
#define MAIN_PLL_SSC_CTRL_PLL_MAIN_DISABLE_SSCG_SHIFT_U32              (0U)

#define ETH_PLL_CTRL_PLL_ETH_BYPASS_U32                                (0x0003F000UL) /*Bypasses undivided reference clock (FREF or [FREFCMLPFREFCMLN] to respective output BYPASS[5]=1 bypasses the reference clock to FOUT[5] BYPASS[4]=1 bypasses the reference clock to FOUT[4] BYPASS[3]=1 bypasses the reference clock to FOUT[3] BYPASS[2]=1 bypasses the reference clock to FOUT[2] BYPASS[1]=1 bypasses the reference clock to FOUT[1], FOUTCML1P, and (inverted to) FOUTCML1N; when PLLEN=1 BYPASS[0]=1 bypasses the reference clock to FOUT[0], FOUTCML0P and (inverted to) FOUTCML0N; when PLLEN=1 For RESERVED[12]=1, the BYPASS[5:2] control signals can be changed asynchronously without a glitch (for FVCO up to 2.5GHz); the transition lasts up to 8 FPFD periods For RESERVED[12]=0, the BYPASS[5:2] control signals can be changed asynchronously with a potential glitch Truth table for Post Dividers [5:2] PLLEN LOCK FOUTENONLOCK FOUTEN BYPASS FOUT X X X 0 X 0 X 0 1 1 X 0 0 0 0 1 0 0 1 0 0 1 0 (FVCO/POSTDIV or 0) 1 1 X 1 0 FVCO/POSTDIV 1 1 X 1 1 FREF X 0 0 1 1 FREF Truth table for Post Dividers [1:0] PLLEN LOCK FOUTENONLOCK FOUTEN BYPASS FOUT 1 X X 0 X 0 1 0 1 1 X 0 1 0 0 1 0 (FVCO/POSTDIV or 0) 1 1 X 1 0 FVCO/POSTDIV 1 1 X 1 1 FREF 1 0 0 1 1 FREF Please refer to the PLLTS7FFLJFRACH Appnote.pdf for more details regarding initialization of bypass logic in glitch-free mode*/
#define ETH_PLL_CTRL_PLL_ETH_BYPASS_SHIFT_U32                          (12U)
#define ETH_PLL_CTRL_PLL_ETH_FOUTEN_U32                                (0x000003F0UL) /*Bit-wise Post Divide Enable FOUTEN[5] enables FOUT[5] 0 -> FOUT[5] is powered down (output driven high) 1 -> FOUT[5] (Frequency is set by FVCO, VCODIVSEL, POSTDIV5A, POSTDIV5B) FOUTEN[4] enables FOUT[4] 0 -> FOUT[4] is powered down (output driven high) 1 -> FOUT[4] (Frequency is set by FVCO, VCODIVSEL, POSTDIV4A, POSTDIV4B) FOUTEN[3] enables FOUT[3] 0 -> FOUT[3] is powered down (output driven high) 1 -> FOUT[3] (Frequency is set by FVCO, VCODIVSEL, POSTDIV3A, POSTDIV3B) FOUTEN[2] enables FOUT[2] 0 -> FOUT[2] is powered down (output driven high) 1 -> FOUT[2] (Frequency is set by FVCO, VCODIVSEL, POSTDIV2A, POSTDIV2B) FOUTEN[1] enables FOUTCML1P, FOUTCML1N and FOUT[1] 0 -> FOUTCML1P and FOUTCML1N CML positive and negative phase output clocks are powered down (output floats low) FOUT[1] is powered down (output driven high) 1 -> FOUTCML1P and FOUTCML1N CML positive and negative phase output clocks are enabled (Frequency is set by FVCO, VCODIVSEL, POSTDIV2A, POSTDIV2B) FOUT[1] (Frequency is set by FVCO, VCODIVSEL, POSTDIV1A, POSTDIV1B) FOUTEN[0] enables FOUTCML0P, FOUTCML0N and FOUT[0] 0 -> FOUTCML0P and FOUTCML0N CML positive and negative phase output clocks are powered down (output floats low) FOUT[0] is powered down (output driven high) 1 -> FOUTCML0P and FOUTCML0N CML positive and negative phase output clocks are enabled (Frequency is set by FVCO, VCODIVSEL, POSTDIV0PRE, POSTDIV0A, POSTDIV0B)*/
#define ETH_PLL_CTRL_PLL_ETH_FOUTEN_SHIFT_U32                          (4U)
#define ETH_PLL_CTRL_PLL_ETH_FOUTENONLOCK_U32                          (0x00000008UL) /*Enable/Disable Post Divide [5:2] when LOCK = 0 For LOCK = 0 and FOUTENONLOCK = 1, FOUT[5:2] outputs are disabled; BYPASS[5:2] are disabled For LOCK = 0 and FOUTENONLOCK = 0, FOUT[5:2] outputs are controlled by FOUTEN[5:2] and BYPASS[5:2] For LOCK = 1, the state of FOUTENONLOCK doesn¡¯t influence the behavior of FOUTEN[5:2] control inputs, i.e. FOUT[5:2] outputs are controlled by FOUTEN[5:2] and BYPASS[5:2]*/
#define ETH_PLL_CTRL_PLL_ETH_FOUTENONLOCK_SHIFT_U32                    (3U)
#define ETH_PLL_CTRL_PLL_ETH_DSMEN_U32                                 (0x00000004UL) /*Enable Delta-Sigma Modulator 0 -> DSM is powered down (integer mode) 1 -> DSM is active (fractional mode)*/
#define ETH_PLL_CTRL_PLL_ETH_DSMEN_SHIFT_U32                           (2U)
#define ETH_PLL_CTRL_PLL_ETH_DACEN_U32                                 (0x00000002UL) /*Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode) 0 -> Fractional noise canceling DAC is not active (test mode only) 1 -> Fractional noise canceling DAC is active (default mode)*/
#define ETH_PLL_CTRL_PLL_ETH_DACEN_SHIFT_U32                           (1U)
#define ETH_PLL_CTRL_PLL_ETH_PLLEN_U32                                 (0x00000001UL) /*Global enable signal for PLL 0 -> Entire PLL (except scan mode) is powered down (outputs (except SCANOUT) all held at 1¡¯b0) 1 -> Entire PLL is enabled (unless scan mode is turned on SCANMODE =1)*/
#define ETH_PLL_CTRL_PLL_ETH_PLLEN_SHIFT_U32                           (0U)

#define ETH_PLL_DIV1_PLL_ETH_INTIN_U32                                 (0x0FFF0000UL) /*PLL Feedback divide value (32 to 1250 in integer mode, 36 to 1250 in fractional mode)*/
#define ETH_PLL_DIV1_PLL_ETH_INTIN_SHIFT_U32                           (16U)
#define ETH_PLL_DIV1_PLL_ETH_REFDIV_U32                                (0x0000003FUL) /*Reference divide value (1 to 63)*/
#define ETH_PLL_DIV1_PLL_ETH_REFDIV_SHIFT_U32                          (0U)

#define ETH_PLL_FRC_DIV_PLL_ETH_FRACIN_U32                             (0x00FFFFFFUL) /*Fractional portion of feedback divide value*/
#define ETH_PLL_FRC_DIV_PLL_ETH_FRACIN_SHIFT_U32                       (0U)

#define ETH_PLL_SSC_CTRL_PLL_ETH_DIVVAL_U32                            (0x003F0000UL) /*Input divider to set modulation frequency Divide value is 1 for DIVVAL=6¡¯d0 and DIVVAL for DIVVAL>0 Modulation Freq= F clksscg / (DIVVAL * 128)*/
#define ETH_PLL_SSC_CTRL_PLL_ETH_DIVVAL_SHIFT_U32                      (16U)
#define ETH_PLL_SSC_CTRL_PLL_ETH_SPREAD_U32                            (0x00001F00UL) /*Spread Depth Control in 0.1% steps 5¡¯b00001 ¨C> 0.1% 5¡¯b00010 ¨C> 0.2% ... 5¡¯b10000 ¨C> 1.6% ... 5¡¯b11111 ¨C> 3.1%*/
#define ETH_PLL_SSC_CTRL_PLL_ETH_SPREAD_SHIFT_U32                      (8U)
#define ETH_PLL_SSC_CTRL_PLL_ETH_RESETPTR_U32                          (0x00000004UL) /*Active High reset for wave table pointer, Internally synchronized to CLKSSCG 1¡¯b0 ¨C> If modulation is active (RESET=1¡¯b0, DISABLE SSCG=1¡¯b0), INTMOD and FRACMOD are updating based on internal wave table. 1¡¯b1 ¨C> Modulation is stopped and wave table position is reset. INTMOD=INTIN, FRACMOD=FRACIN. Set RESETPTR=1¡¯b1 while Fractional PLL is locking and de-assert after LOCK is established to start modulation*/
#define ETH_PLL_SSC_CTRL_PLL_ETH_RESETPTR_SHIFT_U32                    (2U)
#define ETH_PLL_SSC_CTRL_PLL_ETH_DOWNSPREAD_U32                        (0x00000002UL) /*Downspread control 1¡¯b0 ¨C> Center-Spread 1¡¯b1 ¨C> Downspread*/
#define ETH_PLL_SSC_CTRL_PLL_ETH_DOWNSPREAD_SHIFT_U32                  (1U)
#define ETH_PLL_SSC_CTRL_PLL_ETH_DISABLE_SSCG_U32                      (0x00000001UL) /*Active-High Modulator Bypass Control 1¡¯b0 ¨C> Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1¡¯b1 ¨C> Bypass modulator (INTMOD = INTIN, FRACMOD = FRACIN). Assertion of DISABLE SSCG is asynchronous*/
#define ETH_PLL_SSC_CTRL_PLL_ETH_DISABLE_SSCG_SHIFT_U32                (0U)

#define ETH_PLL_VCO_PLL_ETH_OFFSETCALCNT_U32                           (0x38000000UL) /*Programmable counter for offset calibration loop Selects the number of PFD edges to wait after each offset calibration step. Count is defined as 2OFFS ETCALCNT+5 (e.g. if OFFSETCALCNT =3¡¯d5, the loop will wait 1024 PFD periods before trying a new setting) Default setting is 3¡¯d2*/
#define ETH_PLL_VCO_PLL_ETH_OFFSETCALCNT_SHIFT_U32                     (27U)
#define ETH_PLL_VCO_PLL_ETH_OFFSETCALBYP_U32                           (0x04000000UL) /*Offset calibration bypass 1¡¯b0 - use the skew calibration output (when OFFSETCALEN=1) to set the phase correction 1¡¯b1 - use the OFFSETCALIN[11:0] value (when OFFSETCALEN =1) to set the phase correction*/
#define ETH_PLL_VCO_PLL_ETH_OFFSETCALBYP_SHIFT_U32                     (26U)
#define ETH_PLL_VCO_PLL_ETH_OFFSETFASTCAL_U32                          (0x02000000UL) /*Offset fast calibration enable Set this to 1 for initial calibration if an initial value is not already known Should be set to 0 when calibrating from an initial condition*/
#define ETH_PLL_VCO_PLL_ETH_OFFSETFASTCAL_SHIFT_U32                    (25U)
#define ETH_PLL_VCO_PLL_ETH_OFFSETCALEN_U32                            (0x01000000UL) /*Active-High offset calibration enable Offset calibration reduces static phase offset to reduce deterministic jitter 1¡¯b0 - skew calibration is disabled. Static phase offset is determined by analog matching only. 1¡¯b1 - skew calibration is enabled. Static phase offset is adjusted by sensing phase at the input.*/
#define ETH_PLL_VCO_PLL_ETH_OFFSETCALEN_SHIFT_U32                      (24U)
#define ETH_PLL_VCO_PLL_ETH_VCODIVSEL_U32                              (0x00100000UL) /*Fixed VCO divider 1¡¯b0 - divide by 1 1¡¯b1 - divide by 4*/
#define ETH_PLL_VCO_PLL_ETH_VCODIVSEL_SHIFT_U32                        (20U)
#define ETH_PLL_VCO_PLL_ETH_RESERVED_U32                               (0x000FFFFFUL) /*Input bits reserved for future use RESERVED[0] enables VCO ring selection 1¡¯b0 - VCO ring selection is off (default VCO ring is 10GHz HP) 1¡¯b1 - VCO ring selection is on RESERVED[2:1] VCO ring selection (when RESERVED[0] == 1¡¯b1): 2¡¯b00 - VCO ring 6.4GHz LP 2¡¯b01 - VCO ring 6.4GHz HP 2¡¯b10 - VCO ring 10GHz LP 2¡¯b11 - VCO ring 10GHz HP RESERVED[3] PLL bandwith selection 1¡¯b0 - PLL bandwith selection is off (default value is 3¡¯b011) 1¡¯b1 - PLL bandwith selection is on RESERVED[6:4] PLL bandwith selection (when RESERVED[3] == 1¡¯b1): In int. mode (DSMEN=1¡¯b0) In frac. mode (DSMEN=1¡¯b1 & DACEN=1¡¯b1) 3¡¯b000 - FPFD/43.5 3¡¯b000 - FPFD/31.6 3¡¯b001 - FPFD/36.1 3¡¯b001 - FPFD/27.9 3¡¯b010 - FPFD/30.8 3¡¯b010 - FPFD/25.0 3¡¯b011 - FPFD/25.1 3¡¯b011 - FPFD/22.0 3¡¯b100 - FPFD/22.5 3¡¯b100 - FPFD/20.1 3¡¯b101 - FPFD/19.2 3¡¯b101 - FPFD/18.1 3¡¯b110 - FPFD/16.4 3¡¯b110 - FPFD/16.2 3¡¯b111 - FPFD/14.3 3¡¯b111 - FPFD/14.7 RESERVED[7] enables power selection 1¡¯b0 - power selection is off (default power is 2¡¯b11 - HP) 1¡¯b1 - power selection is on RESERVED[9:8] power selection (when RESERVED[7] == 1¡¯b1): 2¡¯b00 - 25% power 2¡¯b01 - 50% power - default for VCO ring 10GHz LP and VCO ring 6.4GHz LP 2¡¯b10 - 75% power 2¡¯b11 - 100% power - default for VCO ring 10GHz HP and VCO ring 6.4GHz HP RESERVED[11:10] regulated supply voltage selection: 2¡¯b00 - VDDREG = 40/90 of VDDHV (0.8V for VDDHV=1.8V) - default setting 2¡¯b01 - VDDREG = 41/90 of VDDHV (0.82V for VDDHV=1.8V) 2¡¯b10 - VDDREG = 42/90 of VDDHV (0.84V for VDDHV=1.8V) 2¡¯b11 - VDDREG = 43/90 of VDDHV (0.86V for VDDHV=1.8V) RESERVED[12] enables glitch-free change into and from bypass mode 1¡¯b0 - glitch-free functionality is off - default seting 1¡¯b1 - glitch-free functionality is on RESERVED[13] enables bypass mode when PLLEN=1¡¯b0 1¡¯b0 - bypass functionality is off when PLLEN=1¡¯b0 1¡¯b1 - bypass functionality is on when PLLEN=1¡¯b0 RESERVED[19:14] - reserved for future use*/
#define ETH_PLL_VCO_PLL_ETH_RESERVED_SHIFT_U32                         (0U)

#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV3B_U32                         (0x70000000UL) /*Second Post Divider for FOUT[3] (1 to 8) This value can be changed asynchronously without a glitch Actual post divide value is POSTDIV3B+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8 Note that POSTDIV3A >= POSTDIV3B*/
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV3B_SHIFT_U32                   (28U)
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV3A_U32                         (0x07000000UL) /*First Post Divider for FOUT[3] (1 to 8) This value can be changed asynchronously without a glitch Actual post divide value is POSTDIV3A+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8 Note that POSTDIV3A >= POSTDIV3B*/
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV3A_SHIFT_U32                   (24U)
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV2B_U32                         (0x00700000UL) /*Second Post Divider for FOUT[2] (1 to 8) This value can be changed asynchronously without a glitch Actual post divide value is POSTDIV2B+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8 Note that POSTDIV2A >= POSTDIV2B*/
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV2B_SHIFT_U32                   (20U)
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV2A_U32                         (0x00070000UL) /*First Post Divider for FOUT[2] (1 to 8) This value can be changed asynchronously without a glitch Actual post divide value is POSTDIV2A+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8 Note that POSTDIV2A >= POSTDIV2B*/
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV2A_SHIFT_U32                   (16U)
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV1B_U32                         (0x00007000UL) /*Second Post Divider for FOUT[1], FOUTCML1P, and FOUTCML1N (1 to 8) Actual post divide value is POSTDIV1B+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8 Note that POSTDIV1A >= POSTDIV1B*/
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV1B_SHIFT_U32                   (12U)
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV1A_U32                         (0x00000700UL) /*First Post Divider for FOUT[1], FOUTCML1P, and FOUTCML1N (1 to 8) Actual post divide value is POSTDIV1A+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8 Note that POSTDIV1A >= POSTDIV1B*/
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV1A_SHIFT_U32                   (8U)
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV0PRE_U32                       (0x00000080UL) /*Enable Pre-Divide by 2.5 for FOUTCML0P, FOUTCML0N 1¡¯b0 ¨C> Total Postdiv is (1+POSTDIV0A) * (1+POSTDIV0B) 1¡¯b1 ¨C> Total Postdiv is 2.5 * (1+POSTDIV0A) * (1+POSTDIV0B)*/
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV0PRE_SHIFT_U32                 (7U)
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV0B_U32                         (0x00000070UL) /*Second Post Divider for FOUTCML0P and FOUTCML0N (1 to 8) Actual post divide value is POSTDIV0B+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8*/
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV0B_SHIFT_U32                   (4U)
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV0A_U32                         (0x00000007UL) /*First Post Divider for FOUT[0], FOUTCML0P and FOUTCML0N (1 to 8) Actual post divide value is POSTDIV0A+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8*/
#define ETH_PLL_POSTDIV1_PLL_ETH_POSTDIV0A_SHIFT_U32                   (0U)

#define ETH_PLL_POSTDIV2_PLL_ETH_POSTDIV5B_U32                         (0x00007000UL) /*Second Post Divider for FOUT[5] (1 to 8) This value can be changed asynchronously without a glitch Actual post divide value is POSTDIV5B+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8 Note that POSTDIV5A >= POSTDIV5B*/
#define ETH_PLL_POSTDIV2_PLL_ETH_POSTDIV5B_SHIFT_U32                   (12U)
#define ETH_PLL_POSTDIV2_PLL_ETH_POSTDIV5A_U32                         (0x00000700UL) /*First Post Divider for FOUT[5] (1 to 8) This value can be changed asynchronously without a glitch Actual post divide value is POSTDIV5A+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8 Note that POSTDIV5A >= POSTDIV5B*/
#define ETH_PLL_POSTDIV2_PLL_ETH_POSTDIV5A_SHIFT_U32                   (8U)
#define ETH_PLL_POSTDIV2_PLL_ETH_POSTDIV4B_U32                         (0x00000070UL) /*Second Post Divider for FOUT[4] (1 to 8) This value can be changed asynchronously without a glitch Actual post divide value is POSTDIV4B+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8 Note that POSTDIV4A >= POSTDIV4B*/
#define ETH_PLL_POSTDIV2_PLL_ETH_POSTDIV4B_SHIFT_U32                   (4U)
#define ETH_PLL_POSTDIV2_PLL_ETH_POSTDIV4A_U32                         (0x00000007UL) /*First Post Divider for FOUT[4] (1 to 8) This value can be changed asynchronously without a glitch Actual post divide value is POSTDIV4A+1 Example: 3¡¯b000 = divide-by-1 3¡¯b001 = divide-by-2 ... 3¡¯b111 = divide-by-8 Note that POSTDIV4A >= POSTDIV4B*/
#define ETH_PLL_POSTDIV2_PLL_ETH_POSTDIV4A_SHIFT_U32                   (0U)

#define PLL_STA_PLL_ETH_OFFSETCALOUT_U32                               (0x0000FFF0UL) /*Offset Calibration output This is the output of either the offset calibration block (if OFFSETCALBYP=0) or a buffered version of OFFSETCALIN[11:0] (if OFFSETCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration can be bypassed for faster locking. The value changes on the rising edge of FREF, so it can be clocked out on the falling edge of FREF.*/
#define PLL_STA_PLL_ETH_OFFSETCALOUT_SHIFT_U32                         (4U)
#define PLL_STA_PLL_ETH_OFFSETCALLOCK_U32                              (0x00000008UL) /*Offset Calibration settled indicator for the PLL 1¡¯b0 ¨C> Offset calibration not yet settled 1¡¯b1 ¨C> Offset calibration settled*/
#define PLL_STA_PLL_ETH_OFFSETCALLOCK_SHIFT_U32                        (3U)
#define PLL_STA_PLL_ETH_LOCK_U32                                       (0x00000002UL) /*PLL ethernet Lock signal Lock detector can measure frequency accuracy down to 0.8% of programmed target frequency 0.8% is the value of the lock circuit measurement uncertainty Actual frequency will be much closer to the final target. Phase settling is guaranteed by design after 1500 PFD cycles.*/
#define PLL_STA_PLL_ETH_LOCK_SHIFT_U32                                 (1U)
#define PLL_STA_PLL_MAIN_LOCK_U32                                      (0x00000001UL) /*PLL main Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles*/
#define PLL_STA_PLL_MAIN_LOCK_SHIFT_U32                                (0U)

#define PLL_LOCK_MON_PLL_ETH_LOCKNUM_U32                               (0x07FF0000UL) /*PLL ethernet lock monitor lock number*/
#define PLL_LOCK_MON_PLL_ETH_LOCKNUM_SHIFT_U32                         (16U)
#define PLL_LOCK_MON_PLL_MAIN_LOCKNUM_U32                              (0x000007FFUL) /*PLL main lock monitor lock number*/
#define PLL_LOCK_MON_PLL_MAIN_LOCKNUM_SHIFT_U32                        (0U)

#define PLL_CLK_CTRL_PLL_ETH_250M_CLK_EN_U32                           (0x00000020UL) /*FOUT[3](250Mhz) of PLL ethernet output enable*/
#define PLL_CLK_CTRL_PLL_ETH_250M_CLK_EN_SHIFT_U32                     (5U)
#define PLL_CLK_CTRL_PLL_ETH_312P5M_CLK_EN_U32                         (0x00000010UL) /*FOUT[2](312.5Mhz) of PLL ethernet output enable*/
#define PLL_CLK_CTRL_PLL_ETH_312P5M_CLK_EN_SHIFT_U32                   (4U)
#define PLL_CLK_CTRL_MAIN_800M_CLK_SEL_U32                             (0x00000008UL) /*main 800Mhz clock select 0: select OSC input pad 25Mhz clock; 1: select PLL main 800Mhz clock;*/
#define PLL_CLK_CTRL_MAIN_800M_CLK_SEL_SHIFT_U32                       (3U)
#define PLL_CLK_CTRL_MAIN_1200M_CLK_SEL_U32                            (0x00000004UL) /*main 1200Mhz clock select 0: select OSC input pad 25Mhz clock; 1: select PLL main 1200Mhz clock divided from 2400Mhz;*/
#define PLL_CLK_CTRL_MAIN_1200M_CLK_SEL_SHIFT_U32                      (2U)
#define PLL_CLK_CTRL_PLL_MAIN_800M_CLK_EN_U32                          (0x00000002UL) /*FOUTPOSTDIV(800Mhz) of PLL main clock output enable*/
#define PLL_CLK_CTRL_PLL_MAIN_800M_CLK_EN_SHIFT_U32                    (1U)
#define PLL_CLK_CTRL_PLL_MAIN_2400M_CLK_EN_U32                         (0x00000001UL) /*FOUT(2400Mhz)of PLL main clock output enable*/
#define PLL_CLK_CTRL_PLL_MAIN_2400M_CLK_EN_SHIFT_U32                   (0U)

#define SW_CLK_EN0_SW_CLK_EN_U32                                       (0xFFFFFFFFUL) /*switch subsystem clock enable bit[0] switch subsystem R5 core0/1 clock enable bit[1] switch subsystem R5 core2/3 clock enable bit[2] switch subsystem R5 core4/5 clock enable bit[3] switch subsystem R5 nic0/1 clock enable bit[4] switch subsystem R5 nic2/3 clock enable bit[5] switch subsystem R5 nic4/5 clock enable bit[6] switch subsystem R5 APB0/1 clock enable bit[7] switch subsystem R5 APB2/3 clock enable bit[8] switch subsystem R5 APB4/5 clock enable bit[9] switch subsystem GMAC AXI master interface clock enable bit[10] switch subsystem GMAC APB interface clock enable bit[11] switch subsystem EPP AXI interface clock enable bit[12] switch subsystem EPP APB interface clock enable bit[13] switch subsystem PCS APB interface clock enable bit[14] switch subsystem LSP CAN APB clock enable bit[15] switch subsystem LSP work clock enable bit[16] switch subsystem LSP CAN work clock enable bit[17] switch subsystem jiayu axi clock enable bit[18] switch subsystem jiayu merak clock enable bit[19] switch subsystem DMA clock enable bit[20] switch subsystem SRAM0 clock enable bit[21] switch subsystem SRAM1 clock enable bit[22] switch subsystem standby SRAM clock enable bit[23] switch subsystem AHB bus switch clock enable bit[24] switch subsystem system control CSR clock enable bit[31:25] switch subsystem clock enable reserved*/
#define SW_CLK_EN0_SW_CLK_EN_SHIFT_U32                                 (0U)

#define SW_CLK_EN1_LSP_APB_CLK_EN_U32                                  (0x00000040UL) /*switch subsystem LSP APB bus_clock enable*/
#define SW_CLK_EN1_LSP_APB_CLK_EN_SHIFT_U32                            (6U)
#define SW_CLK_EN1_XGMAC_WCLK_EN_U32                                   (0x00000020UL) /*SOC subsystem XGMAC transmit_clock enable*/
#define SW_CLK_EN1_XGMAC_WCLK_EN_SHIFT_U32                             (5U)
#define SW_CLK_EN1_GMAC_WCLK_EN_U32                                    (0x00000010UL) /*switch subsystem GMAC transmit clock enable*/
#define SW_CLK_EN1_GMAC_WCLK_EN_SHIFT_U32                              (4U)
#define SW_CLK_EN1_LSP_PTP_CLK_EN_U32                                  (0x00000008UL) /*switch subsystem LSP CAN ptp_clock enable*/
#define SW_CLK_EN1_LSP_PTP_CLK_EN_SHIFT_U32                            (3U)
#define SW_CLK_EN1_EPP_PTP_CLK_EN_U32                                  (0x00000004UL) /*switch subsystem EPP ptp_clock enable*/
#define SW_CLK_EN1_EPP_PTP_CLK_EN_SHIFT_U32                            (2U)
#define SW_CLK_EN1_XGMAC_PTP_CLK_EN_U32                                (0x00000002UL) /*SOC subsystem XGMAC ptp_clock enable*/
#define SW_CLK_EN1_XGMAC_PTP_CLK_EN_SHIFT_U32                          (1U)
#define SW_CLK_EN1_GMAC_PTP_CLK_EN_U32                                 (0x00000001UL) /*switch subsystem GMAC ptp_clock enable*/
#define SW_CLK_EN1_GMAC_PTP_CLK_EN_SHIFT_U32                           (0U)

#define SW_CLK_SEL0_SW_CLK_SEL0_U32                                    (0xFFFFFFFFUL) /*switch subsystem clock select0 bit[1:0] switch subsystem R5 core0/1 clock select 0: osc input 25Mhz clock 1: 1200Mhz clock 2: 800Mhz clock 3: 400Mhz clock bit[3:2] switch subsystem R5 core2/3 clock select 0: osc input 25Mhz clock 1: 1200Mhz clock 2: 800Mhz clock 3: 400Mhz clock bit[5:4] switch subsystem R5 core4/5 clock select 0: osc input 25Mhz clock 1: 1200Mhz clock 2: 800Mhz clock 3: 400Mhz clock bit[7:6] switch subsystem R5 nic0/1 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock bit[9:8] switch subsystem R5 nic2/3 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock bit[11:10] switch subsystem R5 nic4/5 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock bit[13:12] switch subsystem R5 APB0/1 clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock bit[15:14] switch subsystem R5 APB2/3 clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock bit[17:16] switch subsystem R5 APB4/5 clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock bit[19:18] switch subsystem GMAC AXI master interface clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock bit[21:20] switch subsystem GMAC APB interface clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock bit[23:22] switch subsystem EPP AXI interface clock select 0: osc input 25Mhz clock 1: 800Mhz clock 2: 600Mhz clock 3: 400Mhz clock bit[25:24] switch subsystem EPP APB interface clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock bit[27:26] switch subsystem PCS APB interface clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock bit[29:28] switch subsystem LSP CAN APB clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock bit[31:30] switch subsystem LSP work clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CLK_SEL0_SW_CLK_SEL0_SHIFT_U32                              (0U)

#define SW_CLK_SEL1_SW_CLK_SEL1_U32                                    (0xFFFFFFFFUL) /*switch subsystem clock select1 bit[1:0] switch subsystem LSP CAN work clock select 0: osc input 25Mhz clock 1: 400Mhz clock 2: 200Mhz clock 3: 100Mhz clock bit[3:2] switch subsystem jiayu axi clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock bit[5:4] switch subsystem jiayu merak clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock bit[7:6] switch subsystem DMA clock select 0: osc input 25Mhz clock 1: 400Mhz clock 2: 200Mhz clock 3: 100Mhz clock bit[9:8] switch subsystem SRAM0 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock bit[11:10] switch subsystem SRAM1 clock select 0: osc input 25Mhz clock 1: 600Mhz clock 2: 400Mhz clock 3: 200Mhz clock bit[13:12] switch subsystem standby SRAM clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock bit[15:14] switch subsystem AHB bus switch clock select 0: osc input 25Mhz clock 1: 400Mhz clock 2: 200Mhz clock 3: 100Mhz clock bit[17:16] switch subsystem system control CSR clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock bit[31:18] switch subsystem clock select reserved*/
#define SW_CLK_SEL1_SW_CLK_SEL1_SHIFT_U32                              (0U)

#define SW_CLK_SEL2_PTP_CLK_SEL_U32                                    (0x00007F00UL) /*switch subsystem PTP clock select bit[3:0] ptp_mux_clk select 4'b0xxx: input clock pad ptp_clk 4'b1000: ethernet external port0 MAC receive clock 4'b1000: ethernet external port1 MAC receive clock 4'b1000: ethernet external port2 MAC receive clock 4'b1000: ethernet external port3 MAC receive clock 4'b110x: PLL ETH ouput 125M clock,divide from FOUT[3] 4'b1110: PLL ETH ouput 125M clock,divide from FOUT[3] 4'b1111: safety subsystem exteranl GMAC receive clock bit[5:4] ptp_div_clk divider select 2'b00: ptp_mux_clk 2'b01: ptp_mux_clk/2 2'b10: ptp_mux_clk/4 2'b11: ptp_mux_clk/5 bit[6] 0: OSC input clock 25Mhz 1: ptp_div_clk*/
#define SW_CLK_SEL2_PTP_CLK_SEL_SHIFT_U32                              (8U)
#define SW_CLK_SEL2_APBSW_CLK_SEL_U32                                  (0x00000030UL) /*switch subsystem APB bus switch and lsp apb clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CLK_SEL2_APBSW_CLK_SEL_SHIFT_U32                            (4U)
#define SW_CLK_SEL2_NOC_CLK_SEL_U32                                    (0x0000000CUL) /*switch subsystem NOC clock select 0: osc input 25Mhz clock 1: 800Mhz clock 2: 600Mhz clock 3: 400Mhz clock*/
#define SW_CLK_SEL2_NOC_CLK_SEL_SHIFT_U32                              (2U)
#define SW_CLK_SEL2_CRM_CLK_SEL_U32                                    (0x00000003UL) /*switch subsystem CRM csr clock select 0: osc input 25Mhz clock 1: 200Mhz clock 2: 100Mhz clock 3: 50Mhz clock*/
#define SW_CLK_SEL2_CRM_CLK_SEL_SHIFT_U32                              (0U)

#define MODE_SEL_DEBUG_CLK_SEL_U32                                     (0x00000300UL) /*switch subsystem debug output clock select 2'b00: main 50Mhz clock 2'b01: main 100Mhz clock 2'b10: main 25Mhz clock 2'b11: Ethernet 78.125Mhz clock*/
#define MODE_SEL_DEBUG_CLK_SEL_SHIFT_U32                               (8U)
#define MODE_SEL_XGMAC_SERDES_MODE_U32                                 (0x00000004UL) /*SOC subsystem XGMAC MII connect mode 0: connect XGMII MII and external port0 1: connect XGMII MII and EPP interanl port6*/
#define MODE_SEL_XGMAC_SERDES_MODE_SHIFT_U32                           (2U)
#define MODE_SEL_GMAC_SERDES_MODE_U32                                  (0x00000002UL) /*switch subsystem GMAC MII connect mode 0: connect GMII MII and external port2 1: connect GMII MII and EPP interanl port7*/
#define MODE_SEL_GMAC_SERDES_MODE_SHIFT_U32                            (1U)
#define MODE_SEL_PLL_MAIN_UNLOCK_RST_EN_U32                            (0x00000001UL) /*SOC subsystem PLL main unlock reset total system or not*/
#define MODE_SEL_PLL_MAIN_UNLOCK_RST_EN_SHIFT_U32                      (0U)

#endif